1. Field of the Invention
The present invention relates to arithmetic processing apparatuses and arithmetic processing methods for performing an addition operation of the absolute values of two bit strings having different bit widths.
2. Description of the Related Art
Typical arithmetic operations in a processor, such as a computer, use floating-point numbers, which can represent a wider range of magnitudes using a limited number of bits. A floating-point number is composed of a sign part, an exponent part, and a mantissa part. Arithmetic operations on floating-point numbers involve frequent additions of the absolute values of the exponent part and the mantissa part.
A typical arithmetic processing apparatus includes two adders to perform addition and subtraction operations of two binary numbers A and B. One of the two adders has a carry-in of 0 serving as a third input, and if the binary numbers A and B have the same positive/negative sign, the output of this adder indicates the result of an arithmetic operation. On the contrary, if the binary numbers A and B have different positive/negative signs and the result of the addition is negative, then the output of this adder is inverted to produce the absolute value, which indicates the result of the arithmetic operation.
The other adder has a carry-in of 1 serving as a third input and performs subtraction based on complement representation of number 2. Therefore, if the binary numbers A and B have different positive/negative signs and the result of the addition is positive, the output of this adder indicates the result of the arithmetic operation.
Because floating-point arithmetic apparatuses that include such arithmetic processing apparatuses tend to include larger circuits and consume more power, various structures are being investigated in order to reduce circuit size by, for example, adding an inverter or modifying shift operations. A related art can be found in Japanese Patent Application Laid-open No. 2000-155671.
However, if two binary numbers A and B have different bit widths (i.e., numbers of digits), addition and subtraction operations of such numbers by using an adder pose a problem in that the processing time can be reduced only to a limited extent; because 0s are appended to the higher-bit end of the number with the smaller bit width when performing addition and subtraction operations. For example, if the binary number A has a larger bit width than the binary number B, 0s are appended to the higher-bit end of the binary number B so that both the numbers have the same bit width.
Thus, adders must have a configuration that can handle a binary number with the larger bit width among the binary numbers with differing bit widths. This leads to increase in the overall circuit size of the adders. In addition, arithmetic operations are performed on all bits, including the high-order bits of a binary number with smaller bit width among the binary numbers with differing bit widths even though those high-order bits are all 0s. This leads to extending the processing time.